DATE: 02-17-2012 HOTFIX VERSION: 016 =================================================================================================================================== CCRID PRODUCT PRODUCTLEVEL2 TITLE =================================================================================================================================== 840105 PCB_LIBRARIAN USABILITY PTF subtype is getting changed when Save As option is used in PDV 873075 PSPICE PROBE Decibel of FFT results are incorrect. 938744 ADW COMPONENT_BROWSE Need ability to customize shopping cart columns to include any Part property 943003 SCM REPORTS The dsreportgen command fails with network located project 961530 ALLEGRO_EDITOR INTERACTIV The problem of Display measure command 962157 CONCEPT_HDL CORE Where is the setting for enabling the Enable PSpice Simulator menu? 962206 CONSTRAINT_MGR CONCEPT_HDL Import physical not passing all constraints from the board to frontend 968205 PSPICE DEHDL_NETLISTER Change SPLIT_INST property to PSICE_SPLIT_INST for Quad Switch type of design. 968509 PCB_LIBRARIAN METADATA Incorrect pinlist.txt was generated if DIFF_PAIR_PINS_POS/NEG was set. 969450 LAYOUT TRANSLATORS OrCAD Layout to Allegro Translator crashes 969997 CONSTRAINT_MGR CONCEPT_HDL ERROR(SPCOPK-1053): Cannot find a ppt part that matches the instance pro~ 971193 CONSTRAINT_MGR UI_FORMS Copy and pasting a formula causes the application to crash on windows. 971601 CONSTRAINT_MGR CONCEPT_HDL ERROR(SPCOPK-1053) and WARNING(SPCODD-66) because of directory structure 973398 CONCEPT_HDL OTHER It should be not packaged with error while working the packaging process if the design has a ERROR 973859 PSPICE ENCRYPTION Pspice crashes with encrypted model 973938 PCB_LIBRARIAN VERIFICATION pc.db is missing 974540 CONCEPT_HDL CORE Graphics updates are real slow 974791 F2B DESIGNVARI Variants are not back-annotating to schematic and turning to ? 974818 ALLEGRO_EDITOR NC Backdrilling produces 0 plunges yet no errors reported. 974945 ALLEGRO_EDITOR SKILL Why is axlPolyOperation is giving different result and not working 974946 MODEL_INTEGRIT TRANSLATION ibis2signoise returns the error - Delay measurement fixture must contain V for ECL technology 975396 CONCEPT_HDL CONSTRAINT_MGR Constraints are dropped after migrating from 16.3 to 16.5 975633 ALLEGRO_EDITOR GRAPHICS 'dynamic_layer_visibility' option in 3D Viewer when checked or unchecked should not change (until next change) 975720 ALLEGRO_EDITOR DRAFTING Datum dimension lines not adjusting to text move 975745 ALLEGRO_EDITOR SKILL cdsServIpc different 16.2 vs 16.5 when Allegro exits 976013 CONCEPT_HDL INFRA Power pin connection of FPGA symbol is missing in netlist. 976058 CONCEPT_HDL COPY_PROJECT SCM Copy project does not create the con and dcf files in tbl_1 views 976073 CONCEPT_HDL COPY_PROJECT All the constraint data is lost in the SCM copied design 976160 CONCEPT_HDL CREFER Cref fails due to some Caeviews error in the design 976204 ALLEGRO_EDITOR DRC_CONSTR Application falsely reporting Mechanical Pin Antipad to Shape Spacing DRC 976448 F2B PACKAGERXL ERROR(SPCOPK-1069): Invalid POWER_GROUP property value 976521 ALLEGRO_EDITOR DRC_CONSTR multi-thread update DRC causes the application to crash 976838 SIG_INTEGRITY OTHER Unable to create XNET for highlighted nets on attached database even after assigning proper Signal Models. 977517 F2B PACKAGERXL Export physical fails after update to 16.5 from 16.3 977902 ALLEGRO_EDITOR DATABASE generate module is crashing allegro 978652 ALLEGRO_EDITOR PADS_IN PADS_IN fails with ERROR: Finished with errors. 978744 APD DEGASSING Some shapes will not DeGas on this design 979940 SIP_LAYOUT OTHER SiP Layout Leadframe autobonding with profile selection 981699 CAPTURE HELP Start Page still shows Hotfix 14 after installing Hotfix 15 DATE: 02-03-2012 HOTFIX VERSION: 015 =================================================================================================================================== CCRID PRODUCT PRODUCTLEVEL2 TITLE =================================================================================================================================== 871567 CONSTRAINT_MGR SCHEM_FTB Ability to filter out Single Node Nets from Constraint Manager 921436 ALLEGRO_EDITOR MANUFACT Change in 'decimal place' for new dimension changes the already placed dimension 941433 CONCEPT_HDL COPY_PROJECT 16.5 Copy Project should warn if trying to copy a 16.3 design 954375 ALLEGRO_EDITOR MANUFACT Change dimension accuracy for few instaces of associative dimensioning 961646 PDN_ANALYSIS EMVIEWER EMViewer Help > About shows wrong version 964912 CONCEPT_HDL COPY_PROJECT ASA project crash after using copy project 967223 ALLEGRO_EDITOR MANUFACT Bug:Oval slots orientation in one direction only 968865 SIP_LAYOUT DIE_ABSTRACT_IF load of die abstract fails due to differences between component and symbol 969485 ALLEGRO_EDITOR SHAPE Shape does not update correctly in 16.5 970331 CONSTRAINT_MGR ANALYSIS Impedance worksheet shows a zero value for impedance 970600 SIP_LAYOUT SYMB_EDIT_APPMOD Option in Die Editor to be able to "physically swap" pins 970910 F2B PACKAGERXL Our customer has problem with pin color after pxl 16.5. 970970 SPECCTRA FANOUT Fanout Vias is placed far away from decaps and does not change the Fanout length even when max_length is reduced. 970985 SIP_LAYOUT OTHER Importing a .spd2 database file using NA2 will cause the APD/SiP tool crash 971757 CONCEPT_HDL INFRA Crash while Saving/Packaging the Design 971923 ALLEGRO_EDITOR MANUFACT Allow to change decimal accuracy for dimension instances 972568 CONSTRAINT_MGR UI_FORMS Tools >Excel missing from CM 972821 CONSTRAINT_MGR CONCEPT_HDL connectivity server warning: Unable to add property WEIGHT 973185 SCM CONSTRAINT_MGR ASA2 block not seeing all instances in a package. 973211 ALLEGRO_EDITOR INTERFACES IDX Object Type Change not recognized 973214 ALLEGRO_EDITOR INTERFACES IDX import package keepout height value change assigns incorrect value 973384 CONCEPT_HDL CHECKPLUS The multiple SIG_NAME has to be occurred an ERROR at the SPB16.5. 973514 SIG_INTEGRITY OTHER Mapping error when Ecset is updated to constraint manager from extracted net 973950 ALLEGRO_EDITOR SHAPE Update to smooth crashes application 974533 SIP_LAYOUT OTHER Crashes in Edit > Die Properties and obviously has a setup problem. 974809 ALLEGRO_EDITOR SKILL argument available for hiding a property with function axlDBCreatePropDictEntry is not working 976179 INSTALLATION ISR Installation of ISR S014 to 16.5 on windows is breaking the documentation index DATE: 01-20-2012 HOTFIX VERSION: 014 =================================================================================================================================== CCRID PRODUCT PRODUCTLEVEL2 TITLE =================================================================================================================================== 733285 PSPICE SIMULATOR Enhancement:In server-client installation use existing index file from server 941020 SIP_LAYOUT OTHER Soldermask enhancement 946407 CONSTRAINT_MGR TDD When is it safe to open a 16.5 design in 16.3? 953067 CONCEPT_HDL OTHER Variant Editor "Error/Warning messages" form is unusable 954818 CONCEPT_HDL COMP_BROWSER Replace button turns to Add in component browser when a component replace is done on the schematic 956450 ALLEGRO_EDITOR DRC_CONSTR Analysis always shows analysis failed in uncoupled length in some diffpairs 958259 F2B DESIGNSYNC ds.exe crashes on a big design when accessing the design from network drive 958395 ALLEGRO_EDITOR SHAPE shape voids won't merge 959212 MODEL_INTEGRIT PARSE Attempting to use "Mark qualified" option on DML File results in dmlcheck and Modelsim wanrings. 959940 APD AUTOVOID Void all command gets result as no voids being generated. 960252 PCB_LIBRARIAN CORE Splash screen in PDV prevents showing error message 961634 PDN_ANALYSIS EMVIEWER Cannot launch PDN EMViewer from withing PCB SI 961645 PDN_ANALYSIS EMVIEWER Standalone EMViewer will crash when opening any result file in the form of *.emv file. 961700 ALLEGRO_EDITOR SHAPE dbdoctor reports ERROR(SPMHUT-144): Illegal arc specification 961733 ALLEGRO_EDITOR SKILL Allegro crashes. Appears to have a memory leak. 961758 ALLEGRO_EDITOR DRC_CONSTR DFA check produces no DRC when the dfa bounds are not a rectangle. 961887 CONCEPT_HDL CONSTRAINT_MGR Match Group created from ECSet cannot be deleted in the same session of CM 962552 APD EDIT_ETCH BUG:APD crashing when we try to slideget information but move works fine 962869 CAPTURE STABILITY Capture crashes after RMB click on rotated parallel wires 963232 CAPTURE MACRO Macros not being played in Windows7 963300 ALLEGRO_EDITOR DATABASE Create > Module crashes in 16.5 but not in 16.3 963651 CONSTRAINT_MGR CONCEPT_HDL ECsets are renamed after packaging on linux 963663 CONSTRAINT_MGR ANALYSIS Q- Why the customized worsheet for Diff pair Impedance not analysing at all for this SIP design 963715 SIG_INTEGRITY OTHER Application only adds the bottom conductor thickness for the via z-axis length 964068 ALLEGRO_EDITOR INTERACTIV Allegro crash when using move alt sym mirror alt sym... 964267 CIS PART_MANAGER Capture become non-responsive, working on Part Manager and creating CIS BOM, for large designs 964597 ADW LRM Issue of LRM license checkout after renewal license by 16.5 (ADW15.5_S23+SPB16.3) 966148 APD INTERFACES Character Limit for DIE Files (*.die) Import 966416 F2B PACKAGERXL Cannot package this design 966421 CONCEPT_HDL CORE DEHDL Crash when applying property on components in duplicated blocks 966693 CONCEPT_HDL CORE DEHDL crashes when doing model assignment if CM is open 966795 ADW ROLLBACK rollback utility does not honor -product option from command line 967089 SIG_INTEGRITY OTHER Matchgroups created by ECSet not deleted when ECset is removed from object. 967222 ALLEGRO_EDITOR OTHER PDF export is leaving data off the drawing 967240 SIP_LAYOUT WIREBOND Change default bond fingers selected on multi-site leads during "bond to leads" program 967297 ALLEGRO_EDITOR OTHER Dynamic Fillet&Eliminate unused stacked vias cannot be used as the Miniaturization option. 967576 CONCEPT_HDL CREFER Occurrence location property values do not appear in flattened schematic generated by CreferHDL 968096 ALLEGRO_EDITOR DRC_CONSTR Mechanical Pin to conductor spacing is not followed. 968222 SIP_LAYOUT DIE_EDITOR die pin loses IC net for a co-design die with multiple ports within IO-cell 968358 CIS PART_MANAGER Capture crash on removing a part from subgroup in part manager 969594 CONCEPT_HDL CORE The dcf file is not updated with schematic changes DATE: 12-16-2011 HOTFIX VERSION: 013 =================================================================================================================================== CCRID PRODUCT PRODUCTLEVEL2 TITLE =================================================================================================================================== 875695 SIG_EXPLORER INTERACTIV Enforce Causality check box doesn't work. 927148 CAPTURE PROJECT_MANAGER Capture crashes on creating scehmatic folder with name which already exists in design 938013 CAPTURE NETLIST_OTHER The netlist in RINF Format contained two identical lines for PCB FOOTPRINT 941409 PSPICE PROBE BUG : Search accuracy wrong in new cursor window 945242 SIG_INTEGRITY SIMULATION Unable to select "shapes" in find filter for 'show parasitic ' command 946293 CONCEPT_HDL ARCHIVER Archiver hangs if there is a whitespace at the end of the path of cref.dat 946770 CONCEPT_HDL CORE “View Design” function is missing in Windows Mode after reseting the menus. 950994 CAPTURE NETGROUPS Problem in expanding the netgroup in Auto Connect to Bus function 953530 SIG_INTEGRITY GEOMETRY_EXTRACT Display Parasitics is displaying wrong results for EMS2D Field Solver compared to topology extraction using Probe. 953713 CONCEPT_HDL PAGE_MGMT Random page replacement/duplication in block 953917 CONCEPT_HDL ARCHIVER archcore should handle errors correctly 953971 ALLEGRO_EDITOR MANUFACT NC Drill files not generated correctly when using the option "“separate files for plated/nonplatedholes” 954400 CAPTURE NETGROUPS BUS members of NetGroup are getting converted to Scalars in Export-Import NetGroup. 954498 SCM B2F SCM crashes when importing physical 954623 ALLEGRO_EDITOR EDIT_ETCH Unable to complete connection with Add Connect - related to soldermask to cline check? 954894 ALLEGRO_EDITOR MANUFACT Dimensions disappear when opening database in v16.5 from v16.3 955029 CONCEPT_HDL CORE custom text font size not recognized in symbol view 955133 SIG_INTEGRITY FIELD_SOLVERS The Field solver creates the differential trace model which is reversed T(D1) and T(D2) of bottom side. 955290 CAPTURE DRC Description for UPD0014 missing in the Browse DRC markers window 955299 ALLEGRO_EDITOR DRC_CONSTR drc text to smd pin does not work any more on this database in 16.3 S039 955338 CONCEPT_HDL CHECKPLUS Need to change PART_NAME 955447 SIG_EXPLORER OTHER Model path set in DE HDL Model Assignment not used by SigXP from CM in DE HDL 955740 SIG_INTEGRITY GEOMETRY_EXTRACT Crosstalk with Timing Windows does not work correctly 955749 ALLEGRO_EDITOR MANUFACT show element Info shows symbol dimensions on incorrect subclass 955912 ALLEGRO_EDITOR OTHER Shapes with voids that are exported to PDF have gray filled area over the void 956129 CONCEPT_HDL INFRA DEHDL uprev hierachical design from 16.2 to 16.5 packaging failure. 956373 ALLEGRO_EDITOR NC drawing name doesn't display in the log file 956393 CAPTURE PROJECT_MANAGER "GENERAL" and "TYPE" tabs are missing from "Properties" dialogue box. 956448 PSPICE MODELEDITOR Can not generate a DEHDL symbol from Model Editor, because no Capture license found 956456 CAPTURE NETLIST_OTHER OrTelesis netlist not transferring user properties defined under combined 956489 ALLEGRO_EDITOR MANUFACT dimensions lost when symbol with diemnsions attached to symbol origin placed on board 956603 CONCEPT_HDL OTHER Part Manager "has stopped working" after changing a component 956751 ALLEGRO_EDITOR ARTWORK Import Gerber command does not work correctly 956847 PCB_LIBRARIAN METADATA PDV - Partdeveloper symbol to function linkage broken/changed in 16.5 956987 CAPTURE OTHER Find from "Search toolbar" doesn't gives complete results 956996 CONCEPT_HDL INFRA Correction to ERROR(SPCODD-7): Following Primitive instance causes CM to empty 957009 CAPTURE NETLIST_OTHER Problem getting database property in Mentor PADS PCB netlist 957137 APD DXF_IF DXF out command dose not work correctly. 957167 APD GRAPHICS Highlighting for Static shape with display_nohilitefont environment variable. 957232 SIG_INTEGRITY OTHER Allegro crash during Model Assignment. 957267 CONCEPT_HDL INFRA Packager Error after Import Design 957866 SIP_LAYOUT DATABASE Cavity outline is not getting deleted from symbol file 958010 ALLEGRO_EDITOR REPORTS Wants the ability to extract "Batch" reports from Partition ".dpf" files. 958252 ALLEGRO_EDITOR TESTPREP Resequence testprep with the option - Delete probes too close crashes the design 958253 ALLEGRO_EDITOR REPORTS Shape did not have thermal relief connected to pin but unrouted nets still shows zero. 958433 ALLEGRO_EDITOR DRC_CONSTR False embedded component DRCs 958753 ALLEGRO_EDITOR SHAPE Dynamic shape is getting corrupted in 16.5 959011 ALLEGRO_EDITOR OTHER copy problem of via and cline 959101 ALLEGRO_EDITOR EXTRACT Using extracta with excluding Thermal reliefs 959253 CONCEPT_HDL INFRA Design will not open 959299 APD MODULES Getting ERROR(SPMHDB-279) when trying to update modules placed on the Top side 959884 CONCEPT_HDL INFRA Design Uprev/concept2cm crashes with Application Error/Out of Memory Error. 959909 ALLEGRO_EDITOR SCHEM_FTB Site level propflow.txt file is ignored property is transferred 960067 SIP_LAYOUT PLATING_BAR Creation of plating bar removes "NODRC_ETCH_OUTSIDE_KEEPIN" property from the clines. 960126 SIG_EXPLORER EXTRACTTOP Allegro PCB SI license is used automatically at Topology Extraction of Allegro Physical Viewer. 960143 SIG_INTEGRITY GEOMETRY_EXTRACT Running simulation in Bus sim happened crash while enable Coulpled Via model to S parameter 961349 CONCEPT_HDL HDLDIRECT Motorola designs have broken connectivity compared to 16.3 961816 ALLEGRO_EDITOR INTERFACES Normal Export > DXF fails and offsets the pins of the BGA symbol 962519 SIP_LAYOUT WIREBOND Align option doesn't work for wb_tackpoint fingers DATE: 11-30-2011 HOTFIX VERSION: 012 =================================================================================================================================== CCRID PRODUCT PRODUCTLEVEL2 TITLE =================================================================================================================================== 959581 CAPTURE NETLIST_OTHER PCB Footprint is getting replaced by VALUE in OTHER netlist formats DATE: 11-18-2011 HOTFIX VERSION: 011 =================================================================================================================================== CCRID PRODUCT PRODUCTLEVEL2 TITLE =================================================================================================================================== 735439 PCB_LIBRARIAN CORE PDV Moving line-dot pinshapes by arrow keys breaks the pinshape 894815 CONCEPT_HDL COMP_BROWSER Why does genlibmetadata command give 'Aborted $PROG' Message? 903073 ADW COMPONENT_BROWSE datasheetl_url directive should support a display string for URL 909919 CONCEPT_HDL OTHER Why is the PublishPDF UNIX command line looking for "true" script? 911561 CAPTURE CORRUPT_DESIGN Capture crashes on trying to save the design. 919579 CAPTURE PRINT/PLOT/OUTPU Print mode be selected based on schematic mode 921247 CONCEPT_HDL COMP_BROWSER genlibmetadata.bat file does not have err defined 925182 CAPTURE PROJECT_MANAGER ENH: Feature to run update cache on all the parts in design cache at once. 926858 CONCEPT_HDL CORE Usability- Modify Component dialog forces user to do 'Reset Filters' to see other ppt rows 927657 CAPTURE NETGROUPS Enhancement: Placement of netgroup definitions under design cache list 934684 ALLEGRO_EDITOR MANUFACT The relation between the linear dimension and the symbol breaks. 935836 SCM SCHGEN ASA crashes when generating Flat Document Schematic 937165 SCM SCHGEN Can't generate Schematic 937292 CAPTURE GENERAL Memory usage keeps on growing and finally gets exhausted while search 937322 CONCEPT_HDL CORE Master.tag file alters the sequence of the files and Genview fails 939135 CONCEPT_HDL CORE Unable to uprev a 16.3 Design to 16.5 with DEHDL-L License 940373 CAPTURE TCL_INTERFACE Enhancement: TCL command to add nets to Netgroup 940547 TDA CORE ERROR(SPDWSD-69): highspeed cannot be checked in 940607 SIG_EXPLORER OTHER Inconsistancy in License usage for opening sigxp -orcad 940790 F2B PACKAGERXL User doesn't want to display pin numbers after Export Physical 16.5. 940944 SIG_EXPLORER OTHER Inconsistant license usage while opening Orcad PCB SI using allegro -sq -orcad and allegro -sq 941354 CAPTURE NETGROUPS Enhancement: Option to rename the unnamed NetGroups 941455 ALLEGRO_EDITOR MANUFACT The Dimensioned mechanical symbol when placed in the board does not show all the dimensions. 941863 ALLEGRO_EDITOR EDIT_ETCH Different behavior of design in v16_3 & v16_5 when add connect is executed on a segment thru script 941881 CONCEPT_HDL COMP_BROWSER How can I suppress the dialog from universalbrowser -genlibindex? 942474 CAPTURE NETGROUPS NetGroup member type of last added member must be remembered by Capture 942522 CAPTURE GEN_BOM Export in excel check mark doesn't invoked BOM in Excel 942557 PCB_LIBRARIAN EXPORT_OTHER PDV Export to Capture crash 942569 ALLEGRO_EDITOR MANUFACT Dimension move and change text deletes leaderless balloon 942573 ALLEGRO_EDITOR MANUFACT Balloon type parameter has no effect on leaderless balloon. 942613 CONCEPT_HDL CORE Genview supports only SCHEMATIC/SYMBOL/VERILOG/VHDL views as input type. .xcon not recongnised 943032 SCM OTHER ASA is not passing the correct reuse_module name to Allegro PCB layout. 943401 CAPTURE NETGROUPS Alphabetical ordering of NetGroups in Place NetGroup 944006 ALLEGRO_EDITOR EDIT_ETCH Vias added to shapes behave differently 944367 CONCEPT_HDL OTHER Too late to do Model Assingment in conceptHDL 16.5 944788 ALLEGRO_EDITOR GRAPHICS Oblong Pad shows unexpected lines 945221 CONSTRAINT_MGR RETAIN_CNS CM Conflict Resolution fails on more complex designs using ECSets and constraints 946270 ALLEGRO_EDITOR PLACEMENT The Rotation Type was changed to "Absoute" if the "iangle 90" use at placementedit mode of spb16.5 946350 F2B DESIGNVARI Variant Editor rename function removes all components 946380 F2B DESIGNVARI Some VARIANTX properties are hard some soft - why? 946419 SIG_INTEGRITY SIMULATION Cannot select component on BoardModel for controller in bus setup form 946458 SCM SCHGEN Schematic generator adding an unnecessary page 947667 ALLEGRO_EDITOR PADS_IN Need support for PADS-POWERPCB-V9.3-BASIC 947789 ALLEGRO_EDITOR MENTOR mbs2brd crashes during translation on the attached design. 948110 CONCEPT_HDL CONSTRAINT_MGR Concept HDL craches when opening SigXP from CM 950970 ALLEGRO_EDITOR MANUFACT Unable to generate artwork, dbdoctor fails to fix errors. 951901 ALLEGRO_EDITOR EDIT_ETCH In 16.5 add connect to same net is shoved 951919 ALLEGRO_EDITOR OTHER Exported package symbol soldermask and pastemask padstack locations not the same as original 951926 CONSTRAINT_MGR OTHER What is MaestroNotifyNotSetReport.txt file? 951939 F2B PACKAGERXL Uprev to 16.5 is changing refdes for some pages 951983 CONCEPT_HDL INFRA Problems converting an Allegro design from 16.3 to 16.5 952057 SCM PACKAGER Export Physical does not works correctly from SCM 952217 ALLEGRO_EDITOR GRAPHICS crash when opening 3d viewer in PCB Editor 952634 CONCEPT_HDL CHECKPLUS Checkplus logical rule fails on a design which packages fine in 16.5 953018 APD REPORTS Shape affects Package Report result. 953337 ALLEGRO_EDITOR OTHER Allow netname and padstack names to be visible for testpoint vias when viewed in Allegro PDF Publisher. 953827 ALLEGRO_EDITOR EDIT_ETCH Snake Breakout function crashed Allegro 953918 GRE CORE GRE cannot route second and third row of pad in die symbol. 954055 CONCEPT_HDL CREFER Crefer fails with UNC install path 954920 SIG_INTEGRITY CIRCUIT_BUILDER Each neighbor crosstalk simulation crashes or returns blank report DATE: 11-7-2011 HOTFIX VERSION: 010 =================================================================================================================================== CCRID PRODUCT PRODUCTLEVEL2 TITLE =================================================================================================================================== 658866 ALLEGRO_EDITOR EDIT_ETCH enhancement option - so that Sliding a via inside a pad does not create a cline 928624 ALLEGRO_EDITOR GRAPHICS Layer visibility control for 3D Viewer 934991 SPECCTRA LICENSING Specctra_adv option is not working correctly for PA3100 plus PS3500 license in v16.5 tiering profile 938073 ALLEGRO_EDITOR PLOTTING Plot Page size A0 and A1 with problem 938128 ALLEGRO_EDITOR DRC_CONSTR DRC changes when do update DRC. 938648 ALLEGRO_EDITOR GRAPHICS Enh - Requesting a way such that Package keepout appears transparent in 3D Viewer 940518 SIP_LAYOUT SYMB_EDIT_APPMOD Swap pins command doesn't complete 941426 CONCEPT_HDL COPY_PROJECT Copy Project fails - Updating opf view This can't happen! 941499 ALLEGRO_EDITOR DRAFTING BUG:Limit Tolerance isnot working for Dimensioning 941814 CONCEPT_HDL CREFER CreferHDL crashes during ScheGen 942914 SIG_INTEGRITY OTHER ZAxis delay calculation 943053 ALLEGRO_EDITOR SHAPE Modifying the Board Outline shape will cause the tool to crash 945321 SIP_LAYOUT EXPORT_DATA generation of a xml file from cdnsip for shrunken die 945350 ALLEGRO_EDITOR SHAPE iPick does not work on shape boundary edit. 945449 APD SKILL When they create a new menu entry with skill APD crashes with next menu selection. 946390 ALLEGRO_EDITOR DRAFTING refresh_symbol crash when trying to refresh mech sym that has dimensions 946401 APD EXPORT_DATA stream out gdsII results in shorting of PWR/GND nets due to elongated etch 946819 SIP_LAYOUT DEGASSING Shape degass command 946869 ALLEGRO_EDITOR OTHER Allegro PDF arc representation needs cleaned up 947230 ALLEGRO_EDITOR SKILL Skill execution crash Allegro 16.5 but work correctly with Allegro 16.3 947603 ALLEGRO_EDITOR OTHER Component Properties (Default or User Defined) not transferred to PDF file 950995 SIG_INTEGRITY OTHER Netrev fatal error when importing logic 951123 ALLEGRO_EDITOR INTERFACES IPC fails to output drill hole info in columns 33-37 951557 CONCEPT_HDL CORE Cannot create the entity folder for old plumbing symbol DATE: 10-26-2011 HOTFIX VERSION: 009 =================================================================================================================================== CCRID PRODUCT PRODUCTLEVEL2 TITLE =================================================================================================================================== 945788 CONCEPT_HDL CORE Some component properties on the parts are incorrectly changed after Import Sheet 945789 ADW LRM Some component instances are not updated by LRM even though cache ptf is updated from reference DATE: 10-21-2011 HOTFIX VERSION: 008 =================================================================================================================================== CCRID PRODUCT PRODUCTLEVEL2 TITLE =================================================================================================================================== 906827 ALLEGRO_EDITOR DATABASE Logic > Parts logic does not work correctly. 923346 CONCEPT_HDL CORE Not able to move the reference designators inside hierarchal blocks after uprev to 16.5 926347 ADW COMPONENT_BROWSE Usability- Libflow Part check in comment should end up in Comments attribute for UCB/Designer to see it 929348 F2B BOM Warning 007: Invalid output file path name 929777 CONCEPT_HDL OTHER Component Revision Manager gives internal error 930783 CONCEPT_HDL CORE Painting with groups with default colors 936748 ALLEGRO_EDITOR INTERACTIV "Unplace Component" menu inconsistent between General Edit and Placement Edit Mode. 938143 ALLEGRO_EDITOR CREATE_SYM Why is this Extra Property 'ECSET_MAPPING_ERROR 938281 SIP_RF OTHER export_chips creating bad data when symbol is split and contains V- V+ pins 938812 ALLEGRO_EDITOR SYMBOL Cannot create a BSM with this DRA, errors out but does not state a reason. 939075 CAPTURE TCL_INTERFACE Texts are getting garbled in command window 939193 F2B PACKAGERXL ERROR(SPCODD-439): Connectivity server is unable to load the design. 939199 CONCEPT_HDL DOC "Retain electrical constraint on net" mismatch between schematic (YES) and design (NO) 939346 ALLEGRO_EDITOR SHAPE Shape disappears when updating with variable shape_rki_autoclip set. 939901 CONCEPT_HDL INFRA NET_SPACING_TYPE shows “?” on lower hierarchy level nets after Upreving to 16.5 version. 939918 PSPICE PROBE Print > Preview for output file causes Pspice crash. 940217 CONCEPT_HDL COMP_BROWSER UCB reports 'No Symbol found for the part' 940835 CONCEPT_HDL INFRA Desing package different after uprev to 16.5 where comp instance propeties are lost lost 941125 ALLEGRO_EDITOR DATABASE Performance advisor doesn't skip non plated slot padstacks 941876 SIG_INTEGRITY OTHER Illegal model name cause pxl fail in 16.3 942210 SCM OTHER Is the Project File argument is being correctly passed? 942274 CAPTURE PROJECT_MANAGER Crash on renaming a Design Cache part in Project Manage after doing replace cache 942839 ALLEGRO_EDITOR GRAPHICS Graphics Issue- Pads are not visible 943055 ALLEGRO_EDITOR SKILL axlDBCreatePropDictEntry causes application to crash DATE: 10-21-2011 HOTFIX VERSION: 007 =================================================================================================================================== CCRID PRODUCT PRODUCTLEVEL2 TITLE =================================================================================================================================== 841096 APD WIREBOND Function required which to check wire not in die pad center. 903263 CAPTURE SCHEMATIC_EDITOR ENH: Selecting parent netgroup must select the underlying netgroup bits. 906692 ADW LRM LRM window is always in front when opening a project 912942 APD WIREBOND constraint driven wire bonding 912951 CONCEPT_HDL CONSTRAINT_MGR Need to manage temporary files on Linux systems 915178 SIP_LAYOUT DIE_STACK_EDITOR Die Pad names changing when updating Die in a design 917887 PCB_LIBRARIAN VERIFICATION Part should not be released if the alt_symbols has errors 923315 SIG_INTEGRITY GEOMETRY_EXTRACT crosstalk simulation fails with TMP popup failure 927382 CONCEPT_HDL CHECKPLUS 'Verify Symbol' forces the use of 'Concept_HDL_Studio' license 927664 CONCEPT_HDL CONSTRAINT_MGR Internal Error disposeipsp 930152 CAPTURE NETGROUPS Scalar net names when being connected to net group overlap when connections are made one by one 930180 CIS LINK_DATABASE_PA Visible property position on schematic get reset on "link database part" operation 930188 CAPTURE DATABASE Capture 16.5 crashes in being re-invoked. 930541 CAPTURE NETGROUPS NETGROUP element renaming doesn' renames the associated net ? 930866 PDN_ANALYSIS SETUP OrCAD PCB SI Session crashes when we open PDN Analysis with "OrCAD PCB SI" license. 930926 ALLEGRO_EDITOR GRAPHICS Via and Holes not visible eventhough set to Visible in Color form 931274 ALLEGRO_EDITOR DRC_CONSTR Negative Plane Islands waived DRCs reappear after performing update DRC. 932091 CONCEPT_HDL CORE Prop attached to SIG_NAME property 932255 ALLEGRO_EDITOR GRAPHICS Change in Zoom level makes arc segment to disappear 932292 ADW LRM LRM crashes during Update operation on a customer design 932639 SIG_INTEGRITY OTHER Add Connect command hangs for about 14 seconds and then returns. 932704 APD DEGASSING Shape > Degass never finishes on large GND plane 932871 APD GRAPHICS could not see cursor as infinite 932882 CAPTURE SCHEMATIC_EDITOR Capture crash with FIND command - ISR05 932969 CONCEPT_HDL CORE ConceptHDL crashes when you save the design in 165 > hotfix #05 933024 CAPTURE NETGROUPS Naming restrictions for NetGroup members 933145 F2B PACKAGERXL Add Subdesign list is truncated in Force SubDesign Design Name pulldown 933214 APD ARTWORK Film area report is larger when fillets are removed 933356 CONCEPT_HDL CORE Net prop display size become 0 if it was attached to SIG_NAME prop. 933532 ALLEGRO_EDITOR COLOR Bad color assign and initialisation during creation of new subclass 933549 ALLEGRO_EDITOR OTHER Chart text missing in export PDF file. 934008 ALLEGRO_EDITOR REFRESH refresh symbol updates symbol text to some unexpected values 934031 ALLEGRO_EDITOR DRC_CONSTR Bug : Update DRC removes Waived status for some DRCs 934087 CONCEPT_HDL CORE Opening DEHDL and Model Assignment before design loads causes crash 934396 CAPTURE SCHEMATIC_EDITOR Find operation is not searching power symbols with + or - signs. 934533 F2B DESIGNVARI The Variant Editor errors are not written to the variants.lst file 934811 SIP_LAYOUT UI_FORMS CDNSIP should not hang if contraction value in z-copy command is out-of-bound 934909 SCM UI Require support for running script on loading a design in SCM 935632 CAPTURE SCHEMATIC_EDITOR SHIFT+Mouse wheel scroll(horizontal) of page is not working in Auto Wire Mode. 935794 ALLEGRO_EDITOR SHAPE BUG:Shape not filled in 16.5 but it does in 16.3 935988 ALLEGRO_EDITOR INTERFACES When attempting to downrev this 16.5 design to 16.3 the tool will crash 936056 ALLEGRO_EDITOR DRC_CONSTR place_manual crash while moving mirrrored symbol 936098 ALLEGRO_EDITOR SKILL axlDBCreateCloseShape does not work correctly. 936212 ALLEGRO_EDITOR INTERFACES DXF not created if Blocks created for Symbol and padstack 936797 CONCEPT_HDL COPY_PROJECT Copy Project crash 936808 ALLEGRO_EDITOR DATABASE Allegro crash replace mechanical symbol 936853 CONCEPT_HDL CONSTRAINT_MGR DEHDL crashes when trying to extract net from CM 937087 CIS DESIGN_VARIANT Upreved design becomes very slow in Variant view mode. DELEET THE DESIGN AFTER RESOLVING THE ISSUE 937173 CAPTURE OTHER Wrong license information "UNLICENSED" in Capture >> Help >> About 937290 APD PLATING_BAR Plating Bar checks does not recognize connection made through etchback through shape. 937411 ALLEGRO_EDITOR DATABASE downrev_library reading from one directory and writing to another hangs the command. 938235 SIP_LAYOUT STREAM_IF Die Orientation is not correct after importing a stream file. 938273 ALLEGRO_EDITOR OTHER PDF export is is not opening viewer with ads_sdlog variable set DATE: 09-16-2011 HOTFIX VERSION: 006 =================================================================================================================================== CCRID PRODUCT PRODUCTLEVEL2 TITLE =================================================================================================================================== 820131 CONCEPT_HDL OTHER Moving symbols to other page will make Allegro components unplaced because logical_path changed. 863860 CONSTRAINT_MGR SCHEM_FTB CM should display or Local Interface and Global nets to help defining low level constraints 919822 TDA CORE Cannot configure LDAP to only list the login name 922907 ADW TDA “last_callout_file” directive in the BOM section is empty causes tda for show Access Denied error 924322 ADW COMPONENT_BROWSE Random - No instance properties are added on Add To Design (RMB or double click) from Search Results 924448 F2B DESIGNVARI Design does not complete variant annotation 925584 CONSTRAINT_MGR SCHEM_FTB 16.3 upreved Design passes the SLOT/Function Properties to PCB 927102 ALLEGRO_EDITOR OTHER Question of Conductor Detailed Length Report 927104 F2B DESIGNVARI Tools > Annotate variants crashes when there are ASCII characters in the property values 927142 F2B DESIGNVARI Incorrect pop up asking while executing variant editor from the command line 927166 CAPTURE NETLIST_ALLEGRO ENH: Feature like NET_SHORT in Capture Allegro flow which allows user to short 2 or more power nets 927410 ALLEGRO_EDITOR DATABASE ERROR(SPMHUT-144): Illegal arc specification error when Run DBDoctor 927475 CONCEPT_HDL CORE About forcereset command of nconcepthdl 927498 CONCEPT_HDL CORE Pin_Name starting with minus causes incorrect behavior for $PN display 927608 ALLEGRO_EDITOR PADS_IN Import PADs fails with error message: Failed to close the Allegro database 927637 SCM CONSTRAINT_MGR ASA crashes on change root and also performance is too slow. 928429 SIG_INTEGRITY OTHER Request - Package Wizard to work in PCB SI. 928483 ALLEGRO_EDITOR DRC_CONSTR Running Update DRC removes Via List DRC Error when via is actually not in the list 928738 PSPICE PROBE Y-axis grid settings for multiple plots 928748 PSPICE PROBE Cursor width settings not saved 928779 CONCEPT_HDL CORE Error (1053) occurs on a copied part in SPB165 release 928838 CONCEPT_HDL CONSTRAINT_MGR ECSets not migrated in 16.5 928885 SIG_EXPLORER EXTRACTTOP PCB SI crashes when extracting a net from Probe 929284 CONCEPT_HDL ARCHIVER archive does not create a zip file 929542 SIP_LAYOUT DIE_ABSTRACT_IF net issue of multiple ports of co-design die in SiP 929656 ALLEGRO_EDITOR PADS_IN PADS translation fails with Microsoft Visual C++ Runtime Library error 930063 ALLEGRO_EDITOR TESTPREP Test prep crash Allego when it can not create pin escape 930217 CAPTURE NETGROUPS Net aliases doen't gets assigend to bus bits if bus name is checked in NETGROUP. 930355 SIP_LAYOUT WIREBOND about "wirebond add nonstandard" command 930607 APD OTHER Layer mapping information is reomved from Layer conversion file upon exporting DXF from board file. 930646 ALLEGRO_EDITOR DRAFTING Bug - Adding Linear Dimenstion for ISO standard add the Angle information as well 930894 CAPTURE TCL_INTERFACE PDF export doesn't creates property file if some symbols are used in page name/folder name 930944 ALLEGRO_EDITOR OTHER Setting variable 'appmode' equal to 'none' is not changing the Application Mode when reinvoked 930978 ALLEGRO_EDITOR SCHEM_FTB 3rd party netin error - Pin is connected to net not reconnected no longer happens 931248 ALLEGRO_EDITOR DRC_CONSTR Match Group was removed if member nets became xnets. 931278 CONCEPT_HDL INFRA $PN gets copied when upreving design from 16.2 to 16.5 version 931349 CONCEPT_HDL COMP_BROWSER DEHDL craches and corrupts connectivity file when using Modify command extensivly. DATE: 08-31-2011 HOTFIX VERSION: 005 =================================================================================================================================== CCRID PRODUCT PRODUCTLEVEL2 TITLE =================================================================================================================================== 825848 ALLEGRO_EDITOR SHAPE Shape not filled when edges from 2 RKO shapes touch around mouting hole 837723 CAPTURE PROPERTY_EDITOR Occurrences of external design not related to current root should not show 891079 CONCEPT_HDL CORE DEHDL crashes with large number of commands in Winodws mode 910908 SIG_EXPLORER OTHER Cannot open top if Tx AMI dll name contain more than 2 dot. 914036 CAPTURE LIBRARY ENH: Option to delete a corrupted part from a library and leaving other parts intact in the library. 914679 ALLEGRO_EDITOR INTERACTIV Custom toolbars are not retained when switching between brd to dra and back to brd file using the File > Recent Designs 914870 MODEL_INTEGRIT OTHER mergedml fails to merger 2 DML files from the model integrity 915645 ALLEGRO_EDITOR MANUFACT Allow the user to place the cross-section chart at a desired location 915653 ALLEGRO_EDITOR INTERACTIV unable to delete non-etch shape 915711 ALLEGRO_EDITOR MANUFACT dimensioning tolerancing by limit not working 916321 CAPTURE GEN_BOM letter limitation in include file 916907 CAPTURE SCHEMATICS “Auto Connect to Bus” should place the wire through non-connectivity objects 920327 CONSTRAINT_MGR ANALYSIS The TotalEtchLength predicate in Constraint Manager does not work for a netclass with a bus. 920753 ALLEGRO_EDITOR GRAPHICS If I confirm to padshape with zoom-in after install the s002 It was changed to wrong shape. 921097 ALLEGRO_EDITOR GRAPHICS Padstack seen partail filled when Zoomed in even "static_shapes_fill_solid" is set 921226 ALLEGRO_EDITOR DRAFTING Unable to select Package Geometry class when dimensioning in the symbol editor. 921623 ALLEGRO_EDITOR GRAPHICS Bug : Symbol not visible when zoomed in 16.5 S002 921891 ALLEGRO_EDITOR DRAFTING dimensions are lost after downrev(ing) a SPB 16.5 design with associative dimensions 921937 ALLEGRO_EDITOR COLOR Padstacks with shape symbol are not showing correctly 922066 CONSTRAINT_MGR ANALYSIS Custom measurement Actual not being cleared when layout changes. 922117 PSPICE PROBE Label colors are not correct in Probe 922519 ALLEGRO_EDITOR SKILL add_bviaarray command fails for some clines but not all 923224 ALLEGRO_EDITOR GRAPHICS Thermal flash Display problem in Allegro v16.5 Hotfix S002 923286 CAPTURE DRC DRC markers not reported for undefined RefDes 923362 ALLEGRO_EDITOR PLOTTING Print to Postscript file not correct in 16.5 923416 ALLEGRO_EDITOR PAD_EDITOR Pad Designer crash on clicking on the Arrow before Soldermask_top 923507 CONCEPT_HDL CONCEPT-PCBDW The function of Import Design in the SPB16.5 Design Entry HDL (for data of ADW15.5_S23 + SPB16.3) 923910 CIS PART_MANAGER Copy & Paste operation from Part Manager copies properties only to first section of the part. 923913 CAPTURE PROJECT_MANAGER Capture runs slow on attached design 923937 CONCEPT_HDL CORE Back annotation time significantly increased with the metadata generation on 923949 ALLEGRO_EDITOR INTERFACES Incremental DXF_IN gives 'Invalid subclass' error 924458 SCM OTHER Project > Export > Schematics crashes 924621 ALLEGRO_EDITOR SHAPE Dynamic shapes are disappearing upon updating them to smooth. 925193 SIG_INTEGRITY FIELD_SOLVERS Diffential Impedance (DiffZ0) values computed in the layer stack-up is incorrect 925195 ALLEGRO_EDITOR DRC_CONSTR Incorrect pin to shape DRC error 925338 CONCEPT_HDL CORE This application has requested the Runtime to terminate it in an unusual way 925435 CAPTURE TCL_INTERFACE Capture crashes if “Save design as UPPERCASE” option is disabled. 925530 SIG_INTEGRITY OTHER Why the single line impedance value for Top and Bottom layers are different for this design? 925864 ALLEGRO_EDITOR DRAFTING Ability to add dimensioning to different CLASS/SUBCLASS 925976 ALLEGRO_EDITOR MENTOR mbs2brd fails to import data 926409 SIP_LAYOUT DRAFTING Exporting a 16.5 design to 16.3 will cause the leader/dimesion lines to be removed. 926443 CONCEPT_HDL CONSTRAINT_MGR In new 16.3 "035" ISR Concept2cm will crash with error. 926503 CAPTURE GENERAL Memory leak Capture/Pspice 926553 CONCEPT_HDL CONSTRAINT_MGR CMGR ERROR There is no net in the Cset that has pins matching those in net 1 in the Xnet 926691 ALLEGRO_EDITOR OTHER Crash while Importing Technology File in CM, with Overwrite Constraints. 926887 CONSTRAINT_MGR CONCEPT_HDL Pin pairs lost after Export Physical 927159 CONCEPT_HDL CONSTRAINT_MGR Export Physical fails due to errors in ConCM.log when SIGNAL_MODEL injected property is '' DATE: 08-19-2011 HOTFIX VERSION: 004 =================================================================================================================================== CCRID PRODUCT PRODUCTLEVEL2 TITLE =================================================================================================================================== 785417 CONCEPT_HDL COPY_PROJECT copyprojectui crashes with a Windows runtime error 851044 CAPTURE GEN_BOM "Export BOM report to Excel" does not appear in the Standard Bill of Material Window. 868216 PSPICE MODELEDITOR Encryption of subckt names, internal nodes, comments 870247 PSPICE SIMULATOR Encrypt a model and simulate it, info about inside nodes being dumped in the probe file 877091 CAPTURE SCHEMATICS Save JPEG, GIF, PNG and other image formats in the database in its compressed form 894059 CAPTURE OTHER Enhancement: Adding column in edit>browse>parts window 895902 RF_PCB OTHER Alphanumerical allegro pin numbers are unusable in ADS 2009 Update 1 895919 RF_PCB OTHER Round trip Allegro to ADS to Allegro requirement 903102 ALLEGRO_EDITOR OTHER Zcopy shape command for cline seems not to work correctly. 905562 SIG_INTEGRITY SIGWAVE Noise margin seems not to be measured correctly with Eye Measure function. 909469 SCM TABLE ASA crashes when opening project 909595 APD LOGIC Inconsistency between export die text out and show element after pin swap 911123 CONCEPT_HDL CORE 16.2 Design uprev to 16.5 fails with ERROR SPCOCD-152 911569 CAPTURE EE_INTERSHEET_RE Q: Why is capture assigning incorrect Irefs in attacehd design ? 915657 ALLEGRO_EDITOR OTHER Allegro PDF Publisher Mirror capability 915755 CONCEPT_HDL CONSTRAINT_MGR Cannot view net in SigXP 916062 CAPTURE GENERAL Auto Wire Crashes Capture 916820 F2B OTHER RF create netlist with problem 917967 ALLEGRO_EDITOR REFRESH Update symbol resets refdes location for bottom side components only. 919343 ALLEGRO_EDITOR PLACEMENT Place Manual is crashing the board file 919481 CONCEPT_HDL CHECKPLUS CheckPlus isGlobal function is not working 919510 CONCEPT_HDL PAGE_MGMT takes 10 min to insert page in DE HDL 919976 APD DATABASE Update Padstack to design crashed APD. 920418 SIP_LAYOUT OTHER SiP enhancement to Auto Assign Pin Use to add ability to change the pin use definition 920420 SIP_LAYOUT LOGIC SiP enhancement to Logic Auto Assign Net to display a dialouge Auto Pin Use assignment should be run 920712 ALLEGRO_EDITOR ARTWORK Program has encountered a problem ... error when creating artwork 920763 ALLEGRO_EDITOR ARTWORK Soldermask gerber missing thru-hole pins 920976 ALLEGRO_EDITOR GRAPHICS Question regarding the difference in the behavior of 3D Viewer w.r.t. height_min 920993 ALLEGRO_EDITOR DRC_CONSTR Minimum Metal Spacing Error is detected on Same Net 921727 ALLEGRO_EDITOR DRC_CONSTR Pad Boundary causing P/P drc to adjacent symbol. 922579 CONCEPT_HDL CORE Xcon file gets corrupted upon Save of Hierarchical design with Global nets tied to interface nets 922592 CONCEPT_HDL CORE DE-HDL does not report illegal connection when Global Net tied to interface net using an Port symbol and named 922758 ALLEGRO_EDITOR DATABASE Allegro crashes while placing second mechanical symbol with route keepin 922839 ALLEGRO_EDITOR DFA The DFA drc display is unstable. 923293 ALLEGRO_EDITOR INTERFACES File> Export> IDX is failing for this design while creating an empty error log. 924772 ADW PCBCACHE Import Sheet is not bringing in Parts used in the source pages into target cache ptf DATE: 08-4-2011 HOTFIX VERSION: 003 =================================================================================================================================== CCRID PRODUCT PRODUCTLEVEL2 TITLE =================================================================================================================================== 787414 CAPTURE PROPERTY_EDITOR Part value can’t be moved on schematic if a part has been copied to a new design and not saved yet. 903898 PCB_LIBRARIAN GRAPHICAL_EDITOR PDV move symbol graphics and Undo causes corruption in graphics 904287 ALLEGRO_EDITOR ARTWORK some cline with arc is missed, when creating artwork. 904418 CHANNEL_ANALYS SIMULATION channel analysis sim does not give valid result 905777 SIG_INTEGRITY SIMULATION User gets popup message that halts an analysis until it is acknowledged 906139 SIG_INTEGRITY OTHER Bus sim result were cleared at the next run even if no preference changed. 908680 SIG_INTEGRITY OTHER Extra prop delay due to resistance 909583 ALLEGRO_EDITOR SKILL axlPolyOperation AND operation is not working correctly. 910315 ADW LRM Import Design with ADW causes partmgr and pxl errors 910689 CONCEPT_HDL CONSTRAINT_MGR NO_SWAP_COMP warning after uprev to 16.5 911684 CONCEPT_HDL CONSTRAINT_MGR Attribute Definitions are incompatible for attribute 'HEADER'. when attempting to place in 16.5 912343 APD OTHER APD crash on trying to modify the padstack 912384 PCB_LIBRARIAN CORE PDV Symbol Editor often freezes when moving groups objects by arrow keys 912853 APD OTHER Fillets lost when open in 16.3. 913586 ALLEGRO_EDITOR ARTWORK Cannot create the drill figures in this design. 914009 ALLEGRO_EDITOR DRC_CONSTR Diff impedance worksheet showing almost zero impedance for differential pair in attached testcase. 914110 CONCEPT_HDL OTHER DEHDL 16.5 Uprev overides property values on hierachical blocks 914264 F2B OTHER Cross Probing from DEHDL for global nets present inside block doesn’t highlight in PCB Editor. 914309 CONCEPT_HDL CORE 16.5 DEHDL crash on saving the user design 914558 ALLEGRO_EDITOR ARTWORK Gerber6x00 output creates unpainted niche in a shape 914633 ALLEGRO_EDITOR ARTWORK Artwork failing in v16.5 while the same design when downrev'd to 16.3 is working fine. 914634 ALLEGRO_EDITOR SKILL IsThrough flag for a padstack is reset 914746 ALLEGRO_EDITOR DRC_CONSTR DRC Update repeats takes longer on each successive pass. 914962 ALLEGRO_EDITOR SHAPE Corruption with Shape filling 915583 CONCEPT_HDL CORE performance issues in 16.5 compared to 16.3 915630 PCB_LIBRARIAN OTHER Error when running SI Model Interface Comparison using IBIS models 915742 CONCEPT_HDL HDLDIRECT I get a newgenasym error and crash when trying to save the symbol 916154 SCM NETLISTER scm crashes when exporting physical database to allegro 916448 CAPTURE NETLIST_LAYOUT Capture 16.5 Layout netlist contains errors 916462 ALLEGRO_EDITOR DATABASE Edit>Split_plane>create hangs Allgro PCB Editor 916469 ALLEGRO_EDITOR REPORTS One Unrouted pin does not show in Unconnected Pins Report 916495 ALLEGRO_EDITOR INTERACTIV Pick selects components from invisible (Off ) layer 916889 CAPTURE NETGROUPS How to change unnamed net group name? 917002 ALLEGRO_EDITOR OTHER Allegro PDF Publisher creates extra circles not available on film 917434 APD OTHER Stream out GDSII has more pads in output data. 917739 CONCEPT_HDL INFRA Global Net tied to port is getting split into 2 nets in 16.5, in 16.3 it is treated as a single net 918187 CONSTRAINT_MGR OTHER Missing acGetTotalEtchLength predicate. 918576 CAPTURE DRC Incorrect DRC is reported for visible power pins which are connected to power symbol DATE: 07-24-2011 HOTFIX VERSION: 002 =================================================================================================================================== CCRID PRODUCT PRODUCTLEVEL2 TITLE =================================================================================================================================== 527444 ALLEGRO_EDITOR EDIT_ETCH Slide command needs to be enhanced for same net spacings 583257 ALLEGRO_EDITOR EDIT_ETCH Add Connect and slide command needs to be enhanced for same net spacings. 592956 ALLEGRO_EDITOR EDIT_ETCH Same net traces will not push and/or shove each other. 745285 ALLEGRO_EDITOR EDIT_ETCH Requesting a true "shove" in Route > Slide for Same net routing. 773503 CAPTURE OTHER Doing "Mirror Horizontally" creates extra un-connects or extra junction dots in Capture V16.3. 774270 F2B PACKAGERXL Require to ignore space in Pattern setting to prevent duplicated Refdes. 799984 ALLEGRO_EDITOR INTERACTIV Enhance the Fix command to select just cline segs 809008 CAPTURE SCHEMATIC_EDITOR New nodes get appeared within the design when we select the design and do "Mirror Horizontally". 810058 CAPTURE SCHEMATIC_EDITOR New nodes get appeared within the design when we select the design and do "Mirror Horizontally". 821133 ALLEGRO_EDITOR MANUFACT Output artwork for pad data that are suppressed unconnected pads with Gerber 6x00 format 831710 CAPTURE SCHEMATIC_EDITOR Capture adds extra junctions to design by itself 842410 ALLEGRO_EDITOR EDIT_ETCH Ability to slide with "Shove" for "Same Net" segments/vias. 854971 ALLEGRO_EDITOR INTERACTIV Capability to add cline segment in a temp group 860772 ADW PCBCACHE Save Shopping Cart (pcbcache) is crashing component browser 867842 CAPTURE PROJECT_MANAGER Capture crash with 'Open File Location" 868306 CAPTURE CONNECTIVITY mirror vertically removes junction creates extra nets 882677 EMI RULE_CHECK bypass_plane_split fail if BYPASS_XXXX_EFFECT_DISTANCE 891439 ALLEGRO_EDITOR INTERACTIV moving cline segments 893544 ALLEGRO_EDITOR INTERFACES IPC-D-356A netlist issue with BB vias. 893765 ALLEGRO_EDITOR PARTITION Mail command not sending out email on Linux platforms. 894390 SIP_LAYOUT EXPORT_DATA Generate all balls in the xml file for export to EDI's readPackage command 895933 APD DATABASE Update Symbol shifts the center of the Dynamic Fillet and creating DRCs 896598 ALLEGRO_EDITOR PLACEMENT error message is misleading 897196 CIS LINK_DATABASE_PA Schematic Contents are not shown in CIS window while link Dbase part for parts placed from library 898598 ALLEGRO_EDITOR MENTOR Negative planes from Mentor Board Station not being translated. 899556 ALLEGRO_EDITOR ARTWORK Import artwork seems not to work correctly. 900501 ALLEGRO_EDITOR PLACEMENT "Place Replicate Apply" is showing lot of DRC's during placement of replicated circuit in 16.5 901141 CIS EXPLORER Japanese character appear garbled in CIS explorer window. 901666 CAPTURE OTHER Home page of Flowcad-Switzerland and Flowcal-Poland is not preserved on captre restart on start page 902066 ALLEGRO_EDITOR DRC_CONSTR Shape in Region not follow the constrains 902349 CAPTURE LIBRARY Capture crashes while closing library 902508 F2B PACKAGERXL SPB16.5 Packager-XL consumes much more memory than 16.3 902841 CAPTURE GENERAL Capture Start page does not show 902876 F2B PACKAGERXL Packager fails on the design upreved in 16.5 902959 CONCEPT_HDL HDLDIRECT HDLDirect Error while saving design 903171 PSPICE NETLISTER Why Capture is treating hierarchical power ports as floting nets in complex heirarchy designs? 903713 ALLEGRO_EDITOR PARTITION Placement Replication do not work fine in the Design Partition 903799 SIP_LAYOUT DIE_EDITOR Disappear die pins after exiting co-design die editor 904021 ALLEGRO_EDITOR OTHER Export PDF from SPB 16.5 produces a file not text searchable 904339 CONCEPT_HDL CORE new design crashes using the attached CDS_SITE 904522 F2B PACKAGERXL Part will not package in 16.5 but packages in 16.3 904764 APD OTHER Enhance Scale Factor of Stream Out to support 4 decimal places 904771 ALLEGRO_EDITOR MANUFACT Pin Number display issue. 904853 ALLEGRO_EDITOR GRAPHICS Enhancement for showing Static shape as it was seen in 16.3 905144 CONSTRAINT_MGR ECS_APPLY Min Line Spacing is larger than Primary or Neck Gap less(-) Tolerance but No Warning in CM 905314 F2B PACKAGERXL Import physical causes csb corruption 905337 CONCEPT_HDL CORE ConceptHDL crashes after Import Design process. 905533 ALLEGRO_EDITOR INTERACTIV Pin numbers for components on BOTTOM Side are moved in Preselect mode,when the BOTTOM layer is invisible 905796 CONCEPT_HDL CONSTRAINT_MGR Fujitsu CM issue inaccurate concept2cm diff pair issues 905811 CAPTURE EE_INTERSHEET_RE interesheet references in the form of grid grid page number instead of page number grid 906118 CONCEPT_HDL CONSTRAINT_MGR Cannot open CM if SIGNAL_MODEL value was not assigned in ptf. 906153 ALLEGRO_EDITOR SCRIPTS Unable to run allegro script in batch mode on the attached board. 906182 APD EXPORT_DATA Modify Board Level Component Output format 906200 ALLEGRO_EDITOR DFA Enh- DFA drc invoked in Batch mode returns false constraint value in Show Element 906517 PSPICE PROBE PSpice new cursor window shows incorrect result. 906627 ADW COMPONENT_BROWSE ppt options are not read if ucb is launched from FM. works fine if launched from dehdl. 906647 SIG_INTEGRITY LIBRARY lib_dist creates a signoise.log in current directory (with backup files like ,1 ,2 etc.) on each run 906673 F2B PACKAGERXL Ignore the signal model validity check during packaging 906688 ADW LRM A copy of source design gets created in worklib of target design after 'Import Design' 906750 ALLEGRO_EDITOR PARTITION Importing design partition removes the testpoint reference designation 906874 PSPICE NETLISTER Error less than 2 connections for unconnected hierarchical pin 907095 F2B OTHER Part Manager does not show Error as Undefined when directive ptf_mismatch_exclude_inj_prop is used 907424 ALLEGRO_EDITOR GRAPHICS Allegro add option for pre 16.5 shape display 907490 CAPTURE NETLIST_LAYOUT 16.5 Layout netlist is not correct. It differs form 16.3 layout netlist. 907884 SIP_LAYOUT MANUFACTURING Need to add an "NC" pin text option for "Manufacturing Documentation Display Pin Text" 907885 SIG_INTEGRITY OTHER Matchgroup targets lost when importing netlist to Allegro layout in HF31 907929 CAPTURE TCL_SAMPLE TCL command to delete a property from parts in a library is not working correctly 907933 SIG_INTEGRITY OTHER Single line impedence not working in OrCad PCB Professional 907963 CONCEPT_HDL CORE Design uprev issue when moving from 16.2 to 16.5 908000 SIG_INTEGRITY OTHER Inconsistence z-axis delay reported on Tpoint when define at via location. 908057 CONCEPT_HDL CORE DE HDL crash with the cut and paste of a signal name 908060 CONCEPT_HDL CORE CTRL+LMB Option not working correctly in 16.3 908210 CAPTURE CONNECTIVITY Connection is being lost while dragging a component 908241 CAPTURE DRC DRC error column is blank in DRC markers window in 16.5 908339 RF_PCB BE_IFF_IMPORT mechanical holes VIAFC are not at the right place 908534 SIP_LAYOUT SYMB_EDIT_APPMOD issues with symbol editor and copying pin arrays 908535 F2B DESIGNVARI When I try to view my variant file the variant editor crashes 908595 APD 3D_VIEWER Cadence Design 3D viewer" screen pops up and is all black because the colors have all converted to b 908849 CAPTURE ANNOTATE Getting crash while annotating the attached design 908874 CONCEPT_HDL CORE Part Manager - No Part Found error when using CCR# 775788 feature 909077 CONCEPT_HDL CORE After packaging pin numbers remains invisible even when $PN 909104 ALLEGRO_EDITOR SYMBOL Warning message needs to be modified. It does not save the symbol and also not tell the actual problem. 909417 ALLEGRO_EDITOR REPORTS "report -v upc" returns 'Segmentation fault' on Linux 909635 SIP_LAYOUT DIE_STACK_EDITOR Add Interposer crashes in SiP Layout 909749 ALLEGRO_EDITOR MANUFACT Allegro Crash during dimensioning 909760 SIP_LAYOUT MANUFACTURING Create bond finger solder mask doesn't follow the mask opening as defined in the padstack 909861 F2B PACKAGERXL NetAssembler broken within the latest 16.30.031 910006 CONCEPT_HDL INFRA Motorola design fails to uprev from 16.3 to 16.5, xcon file is getting corrupted. 910141 CAPTURE NETGROUPS Modify NetGroup definition does not update Offpage Connector 910340 ADW LRM Import design in schematic, only 1 page import, the entire block is getting imported. 910678 SIG_INTEGRITY OTHER The Analyze> Model Assignment> Auto setup is not creating/assigning models to discrete components in 16.5 910713 F2B DESIGNVARI Variant Editor crashes when you click web link under Physical Part Filter window. 910936 F2B PACKAGERXL ConceptHDL subdesign net name is inconsistent 911530 ALLEGRO_EDITOR SYMBOL Package Symbol Wizard does not create symbol with the name given 911631 CONCEPT_HDL CORE DEHDL crashes when opening a design 912001 ALLEGRO_EDITOR OTHER option_licenses entries are made in allegro.ini even when not set as default 912459 F2B BOM BOMHDL crashes before getting to a menu 913359 APD MANUFACTURING Package Report shows incorrect data DATE: 06-24-2011 HOTFIX VERSION: 001 =================================================================================================================================== CCRID PRODUCT PRODUCTLEVEL2 TITLE =================================================================================================================================== 293005 ALLEGRO_EDITOR DATABASE Allegro crash when attempting to move mech. symbol 298289 CIS EXPLORER CIS querry gives wrong results 366939 ALLEGRO_EDITOR OTHER Cannot attach refdes on silk subclass with add text 432200 ALLEGRO_EDITOR MANUFACT Fillets with an arc are required for Flexi designs 443447 APD SHAPE Shapes not following the acute angle trim control setting. 473308 PSPICE AA_SENS Passing variables to lower level blocks using subparam 517556 PSPICE AA_SENS Advanced Analysis does not support variables being passed down the hierarchy 548143 ALLEGRO_EDITOR SHAPE Dynamic shpe on Etch TOP will not void properly. 606959 ADW COMPONENT_BROWSE Key properties with blank values are not getting read in shooping cart 616466 ALLEGRO_EDITOR SHAPE Solid shapes are not getting filled 641358 SIP_LAYOUT DIE_STACK_EDITOR Request for Via and Multi Layer Pin support for DIE stack Area (blue region) 644122 SIP_LAYOUT OTHER SiP Layout - xsection - ERROR Adjacent conductive layers are not allowed, but these are diestack layers not conductor 645816 ALLEGRO_EDITOR SHAPE Slide a cline all removes gnd shapes on board 725355 ALLEGRO_EDITOR SHAPE User can not voided Logo correctly. 763569 CONCEPT_HDL CORE Display status of Hide/Show unconnected pins icon in DE HDL UI 770021 CAPTURE BACKANNOTATE Changing pin group property after pin swap resets pin numbers 792126 CAPTURE PROPERTY_EDITOR Attempt to change display for occ prop resets 799014 CONCEPT_HDL CONSTRAINT_MGR concept2cm errors not shown in export physical after hier_write 803147 CIS LINK_DATABASE_PA Link DB part should not change RefDes of multi package part 804240 PSPICE DEHDL Problem in simulation result for a multi-section split part. 809118 CAPTURE NETLISTS ENH to compare two schematic Capture designs 816568 ALLEGRO_EDITOR SHAPE shape disappears when update to smooth.. State no etch 830053 CAPTURE STABILITY DXF export fails if schematic folder name as / 832108 ALLEGRO_EDITOR SHAPE Shape void incorrectly. 833542 CONCEPT_HDL CORE PDF publisher font is NOT WYSIWIG with respect to what seen in DE HDL 835777 CIS DERIVE_NEW_DB_PA For XLS, donot display table as worksheetName$worksheetName to avoid 8012 error 837640 CIS GEN_BOM date format of CIS BOM has broken macros of 16.2 in 16.3 version 844074 APD SPECCTRA_IF Export Router fails with memory errors. 851595 CONCEPT_HDL CORE Pin numbers overlap on the pin and increase in size 852832 CAPTURE BACKANNOTATE Why is Capture crashing with Mentor back annotation? 855015 ALLEGRO_EDITOR OTHER The rats are NOT connecting to the ends of the clines like they should be. 859883 CAPTURE NETLISTS ENH to compare two schematic Capture designs 866009 SIG_INTEGRITY OTHER Net with Pull-up/down should not be used for Diff-pair. 866830 SCM REPORTS Multiple lines added as separator between title block and report header instead of single line 866833 SCM REPORTS Extra indentation is left in the left side of the report when the Line Numbers are set to OFF 868618 SCM IMPORTS Block re-import does not update the docsch and sch view 873402 SIP_LAYOUT LOGIC pin swap for co-design die in SiP 874010 SIG_INTEGRITY OTHER PCB SI crashes when the Xnet is extracted with VARIANT_TO_IGNORE property. 874400 ALLEGRO_EDITOR INTERACTIV Flip mode issue with move command 874966 ALLEGRO_EDITOR INTERFACES Placed mechanical component do not get Ref Des or part number in IDF file 875709 ALLEGRO_EDITOR REPORTS Film area report generated incorrect data at l1 876275 CONCEPT_HDL CONSTRAINT_MGR Constraint Manager not retaining target net 879361 SCM UI SCM crashes when opening project 879496 CONCEPT_HDL OTHER Customer wants to have the tabulation” key as separator in HDL BOM. 879514 PSPICE AA_MC Monte Carlo to handle equation as comp VALUE. 881845 ALLEGRO_EDITOR SHAPE Delete island deletes complete shape 882413 PDN_ANALYSIS PCB_PI PDN Analysis should support routed power nets 882427 PDN_ANALYSIS PCB_PI PDN Analysis target impedance should have a variable multiplier 882567 SIG_INTEGRITY OTHER PCB SI crash if boolean type prop was specified to VARIANT env. 882644 ALLEGRO_EDITOR PLACEMENT PCB Place Replicate Function automatically match Enhancement 883164 ALLEGRO_EDITOR INTERACTIV Vias marked fanout moves away from position when moving component 883224 SIG_INTEGRITY SIMULATION crash while reflection simulation from Constraint Manager 883760 PCB_LIBRARIAN METADATA Incorrectly formatted revision.dat file in the metadata folder 885391 SIG_INTEGRITY SIMULATION RLGC data sampling algorithm and w-element interpolation. 885849 ALLEGRO_EDITOR MANUFACT Silkscreen Audit cannot find Solder mask for the text string 885996 SIG_INTEGRITY OTHER The effect of sn_maxwidthlimit user preference is not seen in cross section impedance calculations 886090 ALLEGRO_EDITOR INTERACTIV Add Arc w/Radius does not snap to grid 887180 CAPTURE SCHEMATIC_EDITOR Signals Navigation window doesnt get updated for Buses 887442 APD SHAPE Copper pour of Dynamic shapes on Top layer which contains many existing signal traces fails. 887578 SCM AUTO_UI Component Replace pops-up the DSPANE-204 Message 887926 SIG_INTEGRITY GEOMETRY_EXTRACT Field solution failed if diff trace on bottom doesn't have reference plane. 888414 SIG_EXPLORER OTHER View Trace Parameter display the thickness of dielectric incorrectly. 888600 CONCEPT_HDL CREFER Cross References not added to Schegen schematic 888679 SIP_LAYOUT SHAPE Can't create the Dynamic shape on layer M1_sig without unwanted horizontal openings appearing. 888804 ALLEGRO_EDITOR OTHER Fillet will become static shape after import from partition board. 888945 CONCEPT_HDL OTHER unplaced component after placing module 889222 ALLEGRO_EDITOR SHAPE Allegro freezes/hangs when adding shape as Polygon with OpenGL ON. 889365 SIG_INTEGRITY GEOMETRY_EXTRACT top/bottom trace impedances extracted to sigxp are wrong in 16.3 889404 ALLEGRO_EDITOR OTHER Incorrect pad size for Top conductor padstack written to column 59-62. 889426 CONCEPT_HDL CHECKPLUS CheckPlus does not find single node net 889636 ALLEGRO_EDITOR MANUFACT Incorrect spelling of "Visibility" in "Film Control" tab in the Artwork Control Form 891235 F2B PACKAGERXL Packager crashes without creating a pxl.log file 891292 ALLEGRO_EDITOR SHAPE arc routing causes weird undesireable shape fill performance 891856 ALLEGRO_EDITOR EDIT_ETCH crash when sliding diff pairs 892375 ALLEGRO_EDITOR PLACEMENT Place Replicate Update disband other groups, irrespective Fixed property added or not. 892455 ALLEGRO_EDITOR SYMBOL Why the overlapping pins are not reported with DRC? 892541 SIG_EXPLORER OTHER Export/Import layerstack through the technology file is changing the layer thickness 892766 APD WIREBOND Excuting Finger moving cannot push aside finger to move with together by shove all mode 892907 ALLEGRO_EDITOR DRC_CONSTR DRC not reported for etch_turn_under_pin violations 892963 ALLEGRO_EDITOR SKILL Bad shape boundary created after axlPolyOperation 'OR 892964 SIP_LAYOUT LOGIC Request that Edit Parts List use Dashes "-". 893295 APD WIREBOND Why move wirebond command does not shove wirebonds? This result in drcs. 893706 CONSTRAINT_MGR OTHER On line DRC hangs on partitioned board 893743 APD EDIT_ETCH Route behavior when spanning pads not as expected. 893783 SIP_LAYOUT OTHER Padstack Design Editing update File menu with a Update to Design and Close instead of 2 operation 894456 ALLEGRO_EDITOR REPORTS Request Net names be added to Propagation delay lines of the DRC report. 894499 SIG_INTEGRITY LIBRARY Tool crashes when moving a cline or selecting the Info icon with OpenGL on. 894582 APD SHAPE When making a dynamic xhatch Via shapes surrounding are abnormal. 895542 SIP_LAYOUT WIREBOND SIP design crashing when moving bond finger using blur mode BLUR_BONDFINGER_PRESRV_CON 895591 ALLEGRO_EDITOR PCAD_IN Importing PCAD file fails to get to the point where we can map layers 895757 APD ARTWORK Import Gerber command could not be imported Gerber data 895964 CONCEPT_HDL CHECKPLUS The CheckPlus command getFileSubstrings is not working correctly 896428 SCM UI Changed Ref Des value not maintained in DEHDL block when part is replaced 896655 CAPTURE EDIF Import/Export Design of Hierarcy design with OrCAD Capture 896846 CAPTURE IMPORT/EXPORT Import edif2cap and capture is crashing 897155 ALLEGRO_EDITOR REPORTS Copper coverage in L2 and L7 looks like the same but film area report had large gap. 897654 CAPTURE EE_INTERSHEET_RE Capture crashes on adding intersheet refernces in abbreviated format on attached design. 899344 RF_PCB BE_IFF_EXPORT dlibx2iff does not provide the component boundary drawing 899629 CONSTRAINT_MGR OTHER ECset for Total Etch Lenght is not present in OrCAD Prof 900175 CONCEPT_HDL CONSTRAINT_MGR Few Xnets are lost from Match Group after packaging and importing the netlist to board file. 900481 CONCEPT_HDL CORE Genview creates a larger symbol without taking the no. of pin in consideration 900813 ALLEGRO_EDITOR DRC_CONSTR With rotated pads, pad (pin - via) soldermask spacing DRC is unreasonable. 900905 PSPICE STABILITY Simsrvr crash and RPC Server unavailable error while running simulation. 901783 CONCEPT_HDL CORE CDS_PART_NAME is annotated on the schematic canvas after running back annotation in 16.5 901909 APD EXPORT_DATA The "package_pin_delay_length.rpt" with Z-axis delay turned on seems wrong 901987 CONCEPT_HDL OTHER SPB16.5 zoom fit does not center the page while ploting the schematic page 902133 CIS OTHER The visible part property value are being shown very distant from part graphics on schematic 902166 SPECCTRA ROUTE Specctra crashes when reading in "bestsave.w" file 902170 ALLEGRO_EDITOR DATABASE Diffpair Issues with OrCad PCB Designer Professional 902177 CONSTRAINT_MGR CONCEPT_HDL Option to view the layer thickness in CM worksheet through worksheet customization 902463 ALLEGRO_EDITOR INTERACTIV APD crashes when we click ( show element ) on certain components 902621 CONCEPT_HDL OTHER Design Differences (vdd) Crashes 902909 APD WIREBOND die to die wirebond crash 902933 ALLEGRO_EDITOR PADS_IN Pads_in fails while reading PADS ASCII file body 903284 PDN_ANALYSIS PCB_STATICIRDROP IRDrop voltage gradients are plotted outside of the PCB outline 903680 CONSTRAINT_MGR ECS_APPLY Constraint Manager not passing all hiearchical member objects to a custom measurement. 904403 ALLEGRO_EDITOR DATABASE Allegro crashes when refreshing module